The present disclosure relates to techniques of controlling a power supply voltage for a memory cell in semiconductor storage devices, such as static random access memory (SRAM) etc.
Advances in miniaturization of semiconductor devices in recent years have been accompanied by an increase in variations in characteristics of transistors included in semiconductor storage devices. The power supply voltage in semiconductor storage devices has been increasingly reduced.
In the background art, the memory cell power supply voltage may be decreased on the row-by-row basis in order to reduce the leakage current of a memory cell. Specifically, a high power supply voltage for memory cells in non-selected rows may be controlled to a voltage value lower than the VDD level (see Japanese Unexamined Patent Publication No. 2006-73165).
Alternatively, in the background art, the memory cell power supply voltage may be decreased on the column-by-column basis in order to increase the write margin of a memory cell while ensuring a sufficient margin for static noise. Specifically, a high power supply voltage for memory cells in a selected column during data write operation may be controlled to a voltage value lower than the VDD level (see Japanese Unexamined Patent Publication Nos. 2006-85786 and 2007-12214).
Alternatively, in the background art, a low power supply voltage for memory cells in a selected column during data write operation may be controlled to a voltage value higher than the VSS level (see Japanese Unexamined Patent Publication No. 2007-234126).
In the technique of Japanese Unexamined Patent Publication No. 2006-85786 supra, no means is provided for supplying charge to the memory cell power supply after the memory cell power supply is decreased during write operation. As a result, the memory cell power supply voltage gradually decreases due to a leakage current. Therefore, during write operation, the memory cell power supply becomes lower than the retention voltage of a memory cell, leading to a problem that data stored or held in memory cells other than those to be written which are connected to the memory cell power supply is destroyed.
In the technique of Japanese Unexamined Patent Publication No. 2007-12214 supra, a voltage lower than the power supply voltage is generated by voltage division performed using two p-type MOS (PMOS) transistors which are connected together in series between the power supply and the ground. However, during write operation, both of the two PMOS transistors are on, and therefore, a through current flows from the power supply to the ground through the memory cell power supply generating portion, resulting in an increase in power consumption.